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JSSC 2013第6期RF & Wireless

Correction to “A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Ante nna for 60 GHz Short-Range Wireless Communication” Toshiya Mitomo, Y ukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Y uta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Y uka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, and Takeshi Tomizawa Manuscript received March 11, 2013; accepted March 11, 2013. Date of cur- rent version May 22, 2013.

IEEE JSSC期刊论文更正：关于2 Gbps吞吐量CMOS收发器芯片组的图19错误修正
2 Gbps吞吐量
CMOS收发器60 GHz无线通信封装天线高吞吐量
▸创新点1：60 GHz短距离无线通信技术，通过高频段实现高速数据传输，显著提升通信速率和带宽利用率，适用于短距离高密度通信场景。
▸创新点2：集成封装天线设计，将天线直接集成到芯片封装中，减少外部组件，优化系统尺寸和性能，提高整体集成度和信号传输效率。
▸创新点3：高吞吐量CMOS收发器，采用先进的CMOS工艺实现2 Gb/s的高吞吐量，降低功耗和成本，同时保持高性能和可靠性。
▸创新点4：系统级优化，通过协同设计天线和收发器，优化信号传输路径，减少信号损耗和干扰，提升整体系统性能和稳定性。
Abstract
” Toshiya Mitomo, Y ukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Y uta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Y uka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, and Takeshi Tomizawa Manuscript received March 11, 2013; accepted March 11, 2013. Date of cur- rent version May 22, 2013. T. Mitomo is with the Wireless System Laboratory Corporate Reserch and Development Center, Toshiba Corpora tion, Kawasaki 212-8582, Japan (e-mail: toshiya.mitomo@toshiba.co