← 返回 JSSC 论文列表JSSC 2013第6期RF & Wireless130nm
Full-Duplex Crystalless CMOS Transceiver With an On-Chip Antenna for Wireless Communication in a Hybrid Engine
一款用于混合动力汽车发动机控制器的全双工无晶振CMOS收发器，集成片上天线。
130nm CMOS, 245mW, 24GHz LO信号, 400MHz时钟
全双工收发器无晶振片上天线ASK调制CMOS
▸创新点1：全双工操作 - 该收发器实现了全双工通信，通过集成双工器（duplexer）有效隔离发射和接收路径，显著提升了通信效率。在输入功率足够时，误码率（BER）低于10^-9，展现了优异的抗干扰能力。
▸创新点2：无晶振设计 - 采用时钟数据恢复（CDR）电路替代传统晶振，生成24 GHz本地振荡信号和400 MHz时钟，降低了系统复杂性和功耗（245 mW），同时提升了集成度。
▸创新点3：集成片上天线 - 首次在单片集成电路中实现片上天线与全双工收发器的协同设计，减少了对外部天线的依赖，提升了系统紧凑性，适用于混合动力汽车引擎控制器的紧凑空间。
▸创新点4：高频ASK调制技术 - 通过振幅键控（ASK）调制在24 GHz高频段实现数据传输，结合CDR技术优化了信号恢复精度，为无线片间通信提供了高可靠性解决方案。
Abstract
A full-duplex transceiver for wireless inter-chip data communication in an engine controller board of hybrid electric ve- hicles is demonstrated. The amplitude shift keying (ASK) trans- ceiver incorporates a clock data recovery circuit for crystalless op- eration as well as for simultaneous generation of a 24-GHz local oscillator signal and a 400-MHz clock for data recovery. The trans- ceiver also integrates an on-chi p antenna and a duplexer. The bit error rate (BER) degradation of RX due to the full duplex opera- tion of transceiver with an on-ch ip antenna is negligible when the input power is greater than n e c e s s a r yt oa c h i e v eaB E R of less than 10 .T h i si st h efirst demonstration of full duplex op- eration for an integrated circuit incorporating an on-chip antenna. The transceiver is fabricated in a 130-nm CMOS technology and consumes 245 mW.