A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling

Abstract

A 6-bit time-to-digital converter that achieves mis- match free operation by using a single delay cell and sampling flip-flop is presented. The proposed TDC was integrated in a digital fractional-N PLL fabricated in a 32-nm digital SoC CMOS process for WiFi/WiMax radi os. The TDC consumes 3 mW from a 1.05-V supply and occupies an area of 0.004 mm .Ad i g i t a l frequency-locked loop is used to track and correct for PVT vari- ations in the TDC and no additional linearization or mismatch calibrations are required. The DPLL uses a 20-bit high dynamic range DAC to drive a VCO in order to effectively realize a DCO with 100-Hz frequency resolut ion. The 2.5-GHz WiFi band LO output is generated from a 40-MHz reference with an integrated phase noise of 35 dBc (10 kHz to 10 MHz) while consuming 21 mW. The worst case spur in the LO output is below 50 dBc without requiring TDC mismatch and linearity calibration.