A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equ

Abstract

A 6-bit time-to-digital converter that achieves mis- match free operation by using a single delay cell and sampling flip-flop is presented. The proposed TDC was integrated in a digital fractional-N PLL fabricated in a 32-nm digital SoC CMOS process for WiFi/WiMax radi os. The TDC consumes 3 mW from a 1.05-V supply and occupies an area of 0.004 mm .Ad i g i t a l frequency-locked loop is used to track and correct for PVT vari- ations in the TDC and no additional linearization or mismatch calibratio