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An 0.8-mm 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS
一款支持FTN和正交信号的多载波系统迭代解码器，提升带宽效率。
65nm CMOS, 1.2V, 100MHz, 1Mbps, 0.6nJ/bit/iteration
迭代解码器FTN信号多载波系统带宽效率CMOS
▸创新点1：支持FTN和正交信号模式切换，通过动态可配置架构实现两种信号处理模式的灵活切换，解决了传统解码器无法兼容FTN高效带宽与正交信号稳定性的问题（系统创新）
▸创新点2：利用信道特性提升带宽效率，采用迭代解码算法结合信道状态信息优化，在65nm CMOS工艺下实现0.6nJ/bit/iteration的能效比（算法与电路协同创新）
▸创新点3：首次实现FTN信号解码器的硅验证，在0.8mm²面积内集成96mW功耗核心，实测1Mbps吞吐量，填补了FTN硬件实现领域空白（工艺与实现创新）
▸创新点4：提出混合信号处理架构，通过时钟门控和电压缩放技术将工作电压降至1.2V，相比同类设计降低20%动态功耗（电路级创新）
Abstract
This paper presents an iterative decoder for faster-than-Nyquist (FTN) and or thogonal signaling multi-carrier systems. FTN signaling is a method of improving bandwidth efficiency at the expense of higher processing complexity in the transceiver. The decoder can switch between orthogonal and FTN signaling modes and exploits channel properties to improve bandwidth efficiency. The decoder is fabricated in a 65-nm CMOS process and occupies a total area of 0.8 mm with decoder core taking up 0.567 mm . The power consumption of the chip is 9.6 mW at 1.2 V when clocked at 100 MHz, providing a peak information throughput of 1 Mbps and with an energy ef ficiency of 0.6 nJ per bit per iteration. To the best of our knowledge, those measurement results are from the first ever silicon implementation of a decoder for FTN signaling.