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JSSC 2013第7期RF & Wireless65nmPLL

Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual C a r r i e rR e c e p t i o ni n6 5n mC M O S Lars Sundström, Member , IEEE, Staffan Ek, Jim Svensson

提出一种用于非连续双载波接收的复杂IF谐波抑制混频器
65nm CMOS, 390MHz时钟频率, 65MHz载波分离
谐波抑制混频器非连续双载波3GPP标准IQ不平衡校正CMOS
采用64个无源单元混频器实现谐波抑制
基于环形振荡器的锁相环时钟控制
支持双载波分离及IQ不平衡校正
Abstract
This paper presents a complex IF mixer for a double conversion receiver architecture to be used for non-contiguous dual carrier reception as speci fied in upcoming releases of 3GPP standards. The complex IF mixer contains four harmonic rejec- tion (HR) mixers, each of which is implemented with 64 passive unit cell mixers, clocked by a ring-oscillator based phase-locked loop and driven by sequencers tha t represent thermometer-coded oversampled sinusoidal LO wave forms. Each HR mixer is fol- lowed by a buffer and a signal distribution network to enable separation of the two carriers as well as IQ-imbalance correction. The complex IF mixer supports reception of two carriers with up to 65 MHz separation using 12 samples per IF LO period and a clock frequency of 390 MHz. The IF mixer is implemented in 65 nm CMOS, has an area of 0.74 mm ,d r a w s2 6m A ,a n dh a sa harmonic conversion lower than dBc per harmonic.