JSSC 2013第8期Data Converters65nmSAR ADCDAC

A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC Si-Seng Wong

提出一种低功耗10位170 MS/s两步二进制搜索辅助时间交错SAR ADC架构。

65nm CMOS, 54.6 dB SNDR, 170 MS/s, 2.3 mW

SAR ADC二进制搜索时间交错低功耗异步逻辑

▸创新点1：采用两步二进制搜索架构，显著降低了DAC的建立时间和功耗，同时提高了转换速度，实现了170 MS/s的高采样率。

▸创新点2：无静态功耗组件（如运放或前置放大器），通过消除静态功耗组件，大幅降低了整体功耗，仅消耗2.3 mW，实现了54.6 dB的SNDR。

▸创新点3：工艺不敏感的异步逻辑减少延迟，通过使用异步逻辑而非最坏情况延迟单元，有效减少了SA循环的延迟，提高了系统的鲁棒性和性能。

▸创新点4：时间交错架构设计，前端5b二进制搜索ADC与后端两个时间交错的6b SAR ADC共享，进一步优化了系统效率和功耗，实现了30.8 fJ/conversion-step的FoM。

Abstract

This paper presents the architecture of a 10b 170 MS/s two-step binary-search assisted time-interleaved SAR ADC. The front-end stage of this ADC is built with a 5b binary-search ADC, which is shared by two time-interleaved 6b SAR ADCs in the second-stage. The design does not use any static component such as op-amp or preampli ﬁer that causes large dissipation of static power. DAC settling speed and power are also relaxed thanks to this architecture. Besides, the pr ocess insensitive asynchronous logic further reduces the delay o f SA loop rather than using worst case delay cells to compensate the process variation problem. The ADC was fabricated in 65 nm CMOS and achieves 54.6 dB SNDR at 170 MS/s with only 2.3 mW of power consumption, leading to a FoM of 30.8 fJ/conversion-step.