← 返回 JSSC 论文列表JSSC 2013第8期Data Converters40-nmPipeline ADCDAC
A 240-mW 21-GSs 52-dB SNDR Pipeline ADC Using MDAC Equalization Jiangfeng Wu Chu
本文介绍了一种用于流水线ADC的MDAC均衡数字校正技术，通过数字FIR滤波器校正MDAC增益和动态误差，显著降低功耗。
240-mW 2.1-GS/s 52-dB SNDR
流水线ADCMDAC均衡数字校正功耗优化CMOS
▸创新点1：MDAC均衡技术，通过数字FIR滤波器校正MDAC增益和动态误差，显著降低MDAC残留放大器带宽需求，从而实现功耗优化。
▸创新点2：数字FIR滤波器校正技术，利用逐次数字FIR滤波器对子ADC输出样本进行处理，有效校正MDAC的增益和动态误差，提升ADC性能。
▸创新点3：功耗降低70%，通过MDAC均衡技术，将MDAC残留放大器功耗从175 mW降至53 mW，显著降低整体ADC功耗至240 mW。
▸创新点4：系统创新，在40-nm CMOS工艺下实现2.1-GS/s的乒乓流水线ADC，达到58 dB SNR和52 dB SNDR的高性能指标。
Abstract
This paper introduces multiplying digital-to-analog
converter (MDAC) equalization, a digital correction technique
for pipeline ADCs that corrects MDAC gain, settling, and other
dynamic errors using successive digital FIR filters operating on
sub-ADC output samples. This technique reduces the required
MDAC residue ampli fier (RA) bandwidth relative to the sampling
frequency, thereby reducing ADC power. MDAC equalization is
demonstrated in a 240-mW 2.1-GS /s ping-pong pipeline ADC in
40-nm CMOS wher