A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS Ehsan Zhian Tabasy , Student Member , IEEE ,A y m a n S h afik, Student Member , IEEE , Shan Huang, Student Member , IEEE , Noah Hae-Woong Y ang , Student Member , IEEE

Abstract

ADC-BASED seria l link receivers are emerging in order to scale data rates over hig h attenuation channels. Embed- ding partial equalization inside the front-end ADC can potentially result in lowering th e complexity of back-end DSP and/or de- creasing the ADC resolution requirement, which results in a more energy-efficient receiver. This paper presents a 6-b 1.6-GS/s ADC with a novel emb edded DFE structure. A redundant cycle technique is proposed for a time-interleaved SAR ADC, which relaxes the DFE feedback critical path delay with low power/area overhead. The 6- bp r o t o t y p eA D Cw i t he m b e d d e do n e - t a pD F Ei s fabricated in an LP 90-nm CMOS process and achieves 4.75-bits peak ENOB and 0.46 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. Enabling the embedded DFE while operating at 1.6 Gb/s over a 46-in FR4 channel with 14-dB loss at Nyquist bandwidth opens a previously closed eye and allows for a 0.2 UI timing margin at a BER .T o tal ADC power including front-end T/Hs and reference buffers is 20.1 mW, and the core time-interleaved ADC occupies 0.24 mm area.