An 8.5–11.5-Gbps SONET Transceiver With Referenceless

Abstract

An 8.5–11.5-Gbps SONET t ransceiver with refer- enceless clock and data recovery (CDR) employing an algorithmic frequency acquisition scheme is presented. Without any training sequence, the frequency acquisition algorithm u tilizes a modi fied digital quadricorrelator frequ ency detector (M-DQFD) incorpo- rated into an LC-based VCO coarse tuning adjustment. M-DQFD eliminates the dead-zone problem associated w ith high dispersion and low SNR links. Fabricated in 65-nm CMOS process, the trans- ceiver complies with stringent OC-192 jitter requirements. With a 400- s acquisition time, the receiver achie ves a high-frequency jitter tolerance of at 10-mVppd input sensitivity. The transmitter output exhibits a random jitter of .T h e transceiver occupies 0.97 mm and consum es 125 mA at 1.0-V supply voltage.