An Energy Efficient 32-nm 20-MB Shared On-Die L3 Cache for Intel® Xeon® Processor E5 Family Min Huang, Moty Mehalel, Ramesh Arvapalli, and

Abstract

An energy ef ficient on-die 20-way set associative L3 c a c h eo fs i z e2 0M Bf o rt h eI n t e l ®X e o n ®p r o c e s s o rE 5f a m i l yi s presented. It is manufactured in the Intel’s 32-nm second gener- ation of high-K dielectric metal gate process with 9-copper metal layers. The L3 cache design uses 0.2119 um cell for the high den- sity big array and 0.2725 um cell for the high performance smaller arrays. The power ef ficiency was achieved by employing advanced power saving schemes and effective Vccmin design techniques. The proposed L3 cache topology seamlessly supports a high density modular and energy efficient designs. The effective and rich redun- dancy design improves both yield and low voltage operations. The L3 cache achieves more than 20–40% energy ef ficiency when com- pared to previous generations and demonstrates wide operating ranges from 1.2 GHz at below 0.7 V to greater than 4.0 GHz at above 1.0 V.