An Energy Efficient 32-nm 20-MB Shared On-Die L3 Cache for Intel Xeon Processor E

Abstract

An energy ef ficient on-die 20-way set associative L3 c a c h eo fs i z e2 0M Bf o rt h eI n t e l ®X e o n ®p r o c e s s o rE 5f a m i l yi s presented. It is manufactured in the Intel’s 32-nm second gener- ation of high-K dielectric metal gate process with 9-copper metal layers. The L3 cache design uses 0.2119 um cell for the high den- sity big array and 0.2725 um cell for the high performance smaller arrays. The power ef ficiency was achieved by employing advanced power saving schemes and effe