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Analysis and Design of mm-Wave Frequency Dividers Based on Dynamic Latches With
基于动态锁存器的毫米波分频器分析与设计，实现宽频带低功耗操作
32nm CMOS, 14-70GHz工作频率, 60%分数带宽, 4.8mW功耗, 55×18μm面积
毫米波分频器动态锁存器负载调制宽频带低功耗
▸创新点1：动态锁存器负载调制技术（方法创新）。通过动态调制负载，显著提高了电荷保持能力，使分频器在14 GHz至70 GHz范围内实现超过60%的分数带宽，同时功耗仅为4.8 mW。
▸创新点2：去除再生交叉耦合对以减少寄生效应（电路创新）。通过移除传统静态CML锁存器中的再生交叉耦合对，最小化了输出节点的寄生效应，从而实现了更高的操作速度和更宽的频率范围。
▸创新点3：时钟输入调制负载以最大化电荷保持（系统创新）。利用输入时钟调制负载，优化了电荷保持时间，提升了分频器在毫米波频段的稳定性和性能。
▸创新点4：32 nm CMOS工艺实现高集成度（工艺创新）。采用32 nm体CMOS工艺，实现了55 µm²的极小面积，同时支持高达70 GHz的操作频率，展示了工艺与设计的协同优化。
Abstract
The availability of wide-b and low-power frequency
dividers is fundamental in transceivers for emerging mm-wave ap-
plications. Up to date injection locked topologies have been inves-
tigated for very high frequency operations but at the price of large
area and limited frequency range. In this work, we investigate a
new class based on dynamic latches with load modul ation. The
proposed latches can be viewed as the evolution of classic static
CML latches where the regenerative cross-coupled pair