← 返回 JSSC 论文列表JSSC 2013第8期Data Converters0.18μm CMOSDAC
Continuous-Time Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC Timir Nandi
提出一种新型SCRZ DAC，结合SC DAC的低时钟抖动敏感性和RZ DAC的低失真特性，显著提升调制器性能。
87.1/84.5/82.3 dB DR/SNR/SNDR, 2 MHz带宽, 16.5 mW功耗, 1.8V电源
连续时间调制器时钟抖动非线性失真SCRZ DAC符号间干扰
▸创新点1：采用SCRZ DAC结构，结合了SC DAC的低时钟抖动敏感性和RZ DAC的低失真特性，有效解决了传统NRZ DAC的ISI问题和RZ DAC的时钟抖动敏感性问题。
▸创新点2：降低时钟抖动敏感性28dB，通过SCRZ DAC的设计，显著提升了系统对时钟抖动的鲁棒性，提高了整体性能。
▸创新点3：结合SC DAC和RZ DAC优势，SCRZ DAC在保持低失真的同时，降低了时钟抖动敏感性，实现了更高的线性度和稳定性。
▸创新点4：在0.18μm CMOS技术下实现，SCRZ DAC的设计在低功耗（16.5 mW）和高性能（DR/SNR/SNDR分别为87.1/84.5/82.3 dB）之间取得了平衡，展示了其在实际应用中的潜力。
Abstract
Conventional continuous-time modulators that use non-return-to-zero (NRZ) f eedback DACs suffer from distor- tion due to intersymbol interference (ISI) and are sensitive to clock jitter. Using a return-to-zero (RZ) DAC solves the problem of ISI, but exacerbates clock jitter sensitivity. The clock jitter sensitivity of an NRZ DAC can be reduced using a switched-capacitor (SC) DAC, but the large peak-to-average ratio of the DAC waveform degrades modulator linearity. In this work, we introduce the switched-capacitor return-to-z ero (SCRZ) DAC, which combines the low clock jitter sensitivity of the SC DAC with the low distor- tion of an RZ DAC. The ef ficacy of the SCRZ principle is borne out by measurement results from a modulator that achieves a DR/SNR/SNDR of 87.1/84.5/82.3 dB in a 2 MHz bandwidth while dissipating 16.5 mW from a 1.8-V supply. The converter, designed in a 0.18- m CMOS technology, reduces clock jitter sensitivity by 28 dB when compared with a traditional RZ DAC.