JSSC 2013第8期RF & Wireless65nm

Design and Analysis of Energy-Ef ﬁcient Reconﬁgurable Pre-Emphasis V oltage-Mode Transmitters Yu e L u, Student Member , IEEE, Kwangmo Jung ,S t u d e n tM e m b e r ,I E E E

提出一种能效优化的可重构预加重电压模式发射机架构，实现10 Gb/s数据传输。

65nm LP CMOS, 1.2V, 10 Gb/s, 200mV差分幅度, 2抽头预加重, 1pJ/bit能效

电压模式发射机预加重能效优化阻抗校准65nm CMOS

▸创新点1：采用并联分流支路实现预加重的电路创新，通过在差分通道并联可控分流支路，显著降低传统预加重结构的功耗开销，实现1pJ/bit的能效指标（10mW@10Gb/s）。

▸创新点2：输出幅度与预加重系数独立可调的系统创新，通过数字控制单元动态调节驱动电流和分流比例，支持200mV差分幅度和2-tap预加重的灵活配置，适应多场景信道补偿需求。

▸创新点3：集成在线阻抗校准的方法创新，采用实时反馈机制监测输出阻抗偏差，通过校准算法自动调整驱动管尺寸，确保在工艺偏差下维持50Ω阻抗匹配，提升信号完整性。

▸创新点4：65nm LP CMOS工艺下的高集成度实现，将幅度控制、预加重、阻抗校准等功能模块集成于单一电压模式发射机架构，芯片面积优化率达行业领先水平。

Abstract

This paper analyzes the signaling and digital power overhead of pre-emphasis voltage -mode transmitters. Utilizing a shunt branch in parallel with the differential channel to implement pre-emphasis is shown to have the best overall energy-ef ﬁciency. Leveraging this technique, an ef ﬁcient pre-emphasis voltage mode transmitter architecture with output amplitude control, pre-em- phasis coefﬁcient control, and online impedance calibration is pro- posed and demonstrated. A 65 nm LP CMOS implementation of this architecture dissipates 10 mW from a 1.2 V supply when transmitting 10 Gb/s 200 mV differential amplitude data with 2-tap pre-emphasis, achievi n g1p J / b i te n e r g ye fﬁciency.