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JSSC 2013第8期Clocking & PLLs110nm/55nm CMOS

Harmonic Rejection Mixing Techniques Using Clock-Gating

通过时钟门控技术实现高谐波抑制的混频器设计
谐波抑制比超过52dB(第三谐波)、54dB(第五谐波)、55dB(第七谐波),IIP2性能68dBm
谐波抑制时钟门控混频器CMOSIIP2
采用时钟门控技术减少高频器件失配敏感度
实现无需校准或修调的高谐波抑制
改进正交匹配和IIP2性能
Abstract
In this paper, harmonic rejection (HR) mixing tech- niques to obtain a high level of HR are described. This is achieved by reducing the sensitivity to mismatches in devices operating at high frequencies. A design fabricated in a 110-nm CMOS process rejects up to the first 14 local oscillator (LO) harmonics and achieves third, fifth, and seventh HR ratios in excess of 52, 54, and 55 dB, respectively, without any calibration or trimming. This mixer also rejects flicker noise and has improved quadratu