JSSC 2013第9期Data Converters65nmFlash ADCNeural Network Accelerator

A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS Chi-Hang Chan, Student Member , IEEE,Y a n Z h u, Member , IEEE, Sai-Weng Sin ,S enior Member , IEEE

本文提出了一种采用65nm CMOS工艺的5位1.25GS/s电容折叠式闪存ADC，通过电容折叠技术和校准方案实现低功耗和高精度。

5-bit, 1.25 GS/s, 595μW, 0.007mm², DNL 0.67 LSB, INL 0.47 LSB, ENOB 4.8b

ADC电容折叠高速低功耗校准

▸创新点1：电容折叠技术实现四倍折叠因子（方法创新）。该技术通过创新的电容网络设计，在不增加静态功耗的前提下实现了信号路径的四倍折叠，显著降低了输入电容至80fF，同时保持了1.25GS/s的高采样率。

▸创新点2：动态功耗优化设计（电路创新）。采用纯动态功耗的电容折叠架构，相比传统静态电流型折叠电路，在1V电源电压下实现595μW的总功耗，使能效比（FoM）达到17fJ/conversion-step的领先水平。

▸创新点3：多维度校准方案（系统创新）。集成折叠误差校准和比较器阈值校准技术，通过数字辅助校正将DNL和INL分别优化至0.67LSB和0.47LSB，解决了高频下非线性失配问题。

▸创新点4：微型化面积实现（工艺创新）。在65nm CMOS工艺中仅占用0.007mm²核心面积，通过紧凑型电容阵列布局和校准电路复用技术，达成芯片间一致性（10个芯片平均ENOB 4.8bit）。

Abstract

This paper presents a 5-bit 1.25-GS/s folding ﬂash ADC. The prototype achieves a folding factor of four with a capacitive folding technique that only consumes dynamic power. Incorporated with various calibration schemes, folding errors and the comparator’s threshold i naccuracies are corrected, thus allowing a low input capacitance of 80 fF. The design is fabricated using 65-nm digital CMOS technology and occupies 0.007 mm . The maximum DNL and INL post calibration are 0.67 and 0.47 LSB, respectively. Measurement results show that the ADC can achieve 1.25 GS/s at 1-V supply with a total power consumption of 595 W. In addition, it exhibits a mean ENOB of 4.8b at dc among ten chips, which yields an F oM of 17 fJ/conversion-step.