A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simul

Abstract

A post-process carrier injection scheme for 6T-SRAM is proposed. The proposed scheme pinpoints and simultaneously repairs only cells that have low read disturb margin by injecting electrons to the strong pass gate transistor. Compared with the con- ventional electron injection scheme that injects electrons to either side of the pass gate transistor o f all cells, the proposed scheme achieves 57% less BL delay, 31% less read energy, 32 ~ 256 times shorter injection time and 3% are a reduction. Th