A 75-µW, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering V aibhav Karkare, Student Member , IEEE

Abstract

Energy-efficient spike-sorting DSPs are necessary to allow for the real-time processing of multi-channel, wireless, implantable neural recordings. Online, unsupervised clustering forms an integral part of on-chip spike sorting. However, pre- vious spike-sorting DSPs did not include unsupervised clustering due to the large memory required for its implementation. We demonstrate the first multi-channel spike-sorting DSP chip that includes online, unsupervised clus tering. On-chip clustering has been made possible by using a two-stage implementation of an online clustering algorithm, a no ise-tolerant distance metric, and selectively clocked high-V register banks. The 16-channel spike-sorting chip, implemented in a 65-nm CMOS process, has a power dissipation of 75 µW at a supply voltage of 270 mV. The implementation of on-chip clustering provides a 240x reduction in the output data rate, which is 3x higher than the data-rate reduction obtained from previous spike-sorting DSP chips.