← 返回 JSSC 论文列表JSSC 2013第9期Data Converters65nmDelta-Sigma ADCNeural Network Accelerator
A 81-dB Dynamic Range 16-MHz Bandwidth Modulator Using Background Calibration Su-Hao Wu, Student Member , IEEE
采用65nm CMOS技术的四阶离散时间ΔΣ调制器，通过背景校准实现高动态范围与带宽。
81dB动态范围/16MHz带宽/94mW功耗
ΔΣ调制器背景校准噪声泄漏高动态范围CMOS
▸创新点1：双二阶环路级联结构 - 采用两个二阶离散时间Delta-Sigma调制器级联的方法，有效提高了系统的稳定性和噪声整形性能，同时降低了设计复杂度。这种结构在1.1 GHz采样率和16.67 MHz输入带宽下实现了81 dB的动态范围。
▸创新点2：背景数字校准技术 - 通过数字校准技术在后台运行，无需中断正常操作，校正了积分器的极点并最小化了量化噪声泄漏。这种技术显著提高了系统的精度和可靠性，同时降低了组件匹配的要求。
▸创新点3：量化噪声泄漏最小化 - 通过噪声泄漏校准技术，有效减少了第一环路的量化噪声泄漏，从而提升了信号的信噪比（74.32 dB）和动态范围（81 dB）。这一技术在高性能调制器中具有重要应用价值。
▸创新点4：低复杂度高速运算放大器设计 - 使用直流增益仅为10的高速运算放大器，在1V电源电压下实现了94 mW的低功耗，同时保持了高性能。这种设计在65 nm CMOS工艺下实现了高速度和低功耗的平衡。
Abstract
A fourth-order discrete-time delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. It com- bines low-complexity circuits and digital calibrations to achieve high speed and high performance. The DSM is a cascade of two second-order loops. It has a sampling rate of 1.1 GHz and an input bandwidth of 16.67 MHz with an oversampling ratio of 33. It uses high-speed opamps with a dc gain of only 10. Two different types of digital calibrations are used. Wefirst employ the integrator leakage calibration to correct the poles of the integrators. We then apply the noise leakage calibration to minimize the leaking quantiza- tion noise from the first loop. The noise leakage calibration also relaxes the component-matching r equirements. Both calibrations can operate in the background without interrupting the normal DSM operation. The chip’s measur ed signal-to-noise-and-distor- tion ratio and dynamic range are 74.32 and 81 dB, respectively. The chip consumes 94 mW from a 1 –V supply. The active area is 0.33 0.58 mm .