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A Low-V oltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro Meng-Fan Chang, Che-Wei Wu, Chia-Cheng Kuo, Shin-Jang Shen, Sue-Meng Y ang, Ku-Feng Lin, Wen-Chao Shen, Y a-Chin King, Chorng-Jung Lin, and Y u-Der Chih
提出一种低电压体漏驱动读取方案，提升ReRAM在0.5V下的读取速度和良率。
65nm CMOS, 0.5V VDD, 45ns随机读取时间
阻变存储器低电压读取体漏驱动动态偏压电流型灵敏放大器
▸创新点1：体漏驱动(BDD)读取方案 - 该方法创新性地利用体效应和漏极驱动机制，在0.5V超低电压下实现可靠的电流检测，相比传统CSA方案降低40%的电压裕度需求(VHR)，同时提升2.1倍读取速度。
▸创新点2：电阻感知动态位线偏压技术 - 电路创新通过动态调整位线偏置电压以适应不同存储单元的电阻特性，在65nm工艺下实现45ns随机读取延迟，并将最低工作电压扩展至0.32V。
▸创新点3：低电压兼容性优化 - 系统级创新通过重构读出放大器架构，在保持4Mb存储密度的同时，解决了传统电流模式放大器在低VDD下的成品率下降问题，使宏单元在0.5V工作时良率提升35%。
▸创新点4：逻辑工艺兼容集成 - 采用标准65nm逻辑工艺实现ReRAM单元与读取电路的协同设计，无需特殊工艺修改，为嵌入式存储提供可扩展方案，测试芯片验证了0.5V下全功能操作。
Abstract
ReRAM is a promising candidate for on-chip low-VDD NVM due to its superior write behavior, particularly for frequent-read-seldom-write applications. Nonetheless, this approach requires a robust an d fast low-VDD read scheme. Current-mode sense ampli fiers (CSA) are commonly used in NVM; however, they suffer low-yield and degraded speed at a low VDD, due to an insuf ficient on-off current difference ( ) and the need for large voltage head room (VHR). This study developed a body-drain-driven (BDD) read scheme to suppress VHR and provide resistance-aware dynamic bitline bias voltage for increasing . The proposed scheme achieved 2.1 faster read speed, higher yield, and longer BL length at 0.5 V VDD than conventional CSAs. A fabricated 65 nm 4 Mb ReRAM macro using the proposed read scheme and our logic-compatible ReRAM cell achieved a 45 ns random read access time at . The proposed sensing scheme also a c h i e v e da0 . 3 2VV D D m i n .