A Spur-Frequency-Boosting PLL With a 74 dBc Reference-Spur Suppression in 90 nm

Abstract

An architectural solution for designing a low-refer- ence-spur PLL is proposed. A spur-frequency boosting block is in- serted between the phase-frequency detector and the charge pump to boost the charge pump input frequency. Hence, the spur at the reference frequency is eliminated and is frequency-boosted to a higher frequency, , at which the PLL gain is much less resulting in greater suppression. Quantitative analysis of the charge pump spurs is presented to clarify the different tradeoffs affe