A Spur-Frequency-Boosting PLL With a −74 dBc Reference-Spur Suppression in 90 nm Digital CMOS

Abstract

An architectural solution for designing a low-refer- ence-spur PLL is proposed. A spur-frequency boosting block is in- serted between the phase-frequency detector and the charge pump to boost the charge pump input frequency. Hence, the spur at the reference frequency is eliminated and is frequency-boosted to a higher frequency, , at which the PLL gain is much less resulting in greater suppression. Quantitative analysis of the charge pump spurs is presented to clarify the different tradeoffs affecting the output spurs level. The proposed technique breaks the classical trade off between the different PLL parameters. It adds a degree of freedom in PLL design to reduce the reference spur level without reducing neither the loop bandwidth nor the voltage-controlled os- cillator’s gain (K ). A 3.6 GHz PLL prototype is fabricated using UMC 90 nm digital CMOS technology. A −74 dBc refer- ence-spur suppression is measured along with a (K /ω )r a t i o of 16.67 and a ( ω /ω ) ratio of 1/20. The proposed architec- ture provides additional spur suppression of 30 dB compared to a conventional PLL and, to the best of the authors’ knowledge, this PLL provides the best normalized reference-spur rejection in lit- erature. The prototype occupies 0.063 mm².