Abstract
Recently, short-distance high-speed wireless com- munication using a 60 GHz band has been studied for mobile application. To realize higher-speed wireless communication while maintaining low power consumption for mobile application D band (110–170 GHz) is promising since it can potentially provide a wider frequency band. Thus, we have studied D-band CMOS circuits to realize low-power ultr ahigh-speed wireless communi- cation. In the D band, however, since no suf ficient device model is provided, research generally has to start from device modeling. In this paper, a design procedu re for D-band CMOS circuits is overviewed from the device laye r to the system layer, where the architecture is optimized to realize both low power and high data transfer rate. Finally, a 10 Gbps wireless transceiver with a power consumption of 98 mW is demonstrated using the 135 GHz band.