JSSC 2013第10期Memory65nm

A 274-pJbit 177-Gbs Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Fl

65nm CMOS工艺下高效能迭代级联BCH解码器，用于NAND闪存纠错。

65nm CMOS, 17.7 Gb/s, 274 pJ/bit

级联BCH解码NAND闪存高吞吐量能效优化65nm CMOS

▸二维计算和更新校验子以减少片上存储器访问

▸行列解码器统一设计以提高面积效率

▸跳过冗余解码过程以提升吞吐量

Abstract

To improve the reliability of MLC NAND ﬂash memory, this paper presents an energy-ef ﬁcient high-throughput architecture for decoding concatenated-BCH (C BCH) codes. As the data read from the ﬂash memory is hard-decided in prac- tical applications, the proposed CBCH decoding method is a promising solution to achieve both high error-correction capa- bility and energy ef ﬁciency. In the proposed CBCH decoding, the number of on-chip memory acces ses consuming much energy is minimized by computing a