A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory Y oungjoo Lee, Student Member , IEEE, Hoyoung Y oo, Student Member , IEEE,J a ehwan Jung, Student Member , IEEE, Jihyuck Jo, Student Member , IEEE

Abstract

To improve the reliability of MLC NAND flash memory, this paper presents an energy-ef ficient high-throughput architecture for decoding concatenated-BCH (C BCH) codes. As the data read from the flash memory is hard-decided in prac- tical applications, the proposed CBCH decoding method is a promising solution to achieve both high error-correction capa- bility and energy ef ficiency. In the proposed CBCH decoding, the number of on-chip memory acces ses consuming much energy is minimized by computing and updating s yndromes two-dimen- sionally. To achieve an area-ef ficient hardware realization, row and column decoders are uni fied into one decoder and some syndromes are computed when the y are needed. In addition, the decoding throughput is enhanced remarkably by skipping redundant decoding processe s. Based on the proposed CBCH decoding architecture, a prototype chip is implemented in a 65-nm CMOS process to decode the (70528, 65536) CBCH code. The proposed decoder provides a decoding throughput of 17.7 Gb/s and an energy ef ficiency of 2. 7 4p J / b i t ,b e i n gv a s t l ys u p e r i o rt ot h e state-of-the-art architectures.