← 返回 JSSC 论文列表JSSC 2013第10期Power Management40nmNeural Network Accelerator
A 60-GHz Dual-Mode Class AB Power Ampli fier in 40-nm CMOS Dixian Zhao, Student Member , IEEE, and Patrick Reynaert ,S e n i o rM e m b e r ,I E EE
40纳米CMOS工艺下实现的60GHz双模AB类功率放大器,通过新型晶体管布局和中和放大器级优化提升性能。
饱和输出功率17.0dBm(高功率模式),效率30.3%
60GHz功率放大器CMOS双模AB类
▸新型晶体管布局减少寄生效应:通过优化晶体管布局设计,显著降低了毫米波频率下的器件和互连寄生效应,提升了功率放大器的性能和稳定性。
▸中和放大器级与输入变压器协同优化:采用中和放大器级与输入变压器的协同优化设计,有效提高了功率增益和系统稳定性,同时降低了功耗。
▸双模操作提升效率:通过双模(高功率和低功率模式)操作设计,结合Class AB工作模式,显著提升了功率放大器的效率(PAE提升5.3%),并延长了电池寿命。
▸开关技术减少组合器损耗:在低功率模式下,通过开关技术关闭一个单元功率放大器,并短路其输出,有效减少了组合器损耗,进一步提升了系统效率。
Abstract
A 60-GHz dual-mode power ampli fier (PA) is imple- mented in 40-nm bulk CMOS technology. To boost the ampli fier performance at millim eter-wave (mmWave) frequencies, a new transistor layout is proposed to minimize the device and intercon- nect parasitics while the neutralized amplifier stage is co-optimized with input transformer to improve t he power gain and stability. The transformer-based power-combining PA consists of two unit amplifiers, operating in Class AB for better back-off ef ficiency. To further reduce the power consu mption and hence extend battery lifetime, one unit PA is tuned off in low-power mode. A switch is used to short the output of this non-operating unit PA to reduce the combiner loss and improve the ef ficiency. The PA achieves a measured saturated output power of 17.0 dBm (12.1 dBm) and 1-dB compressed power of 13.8 dBm (9.1 dBm) in the high-pow er (low-power) mode. The power-added efficiencies (PAEs) at and are 30.3% and 21.6% respectively for the high-power mode. Compared to Class A, the PA operating in Class A B shows 5.3% improvement in measured PAE at with no compromise in linearity. The PA with the power combiner only occupies an active area of 0.074 mm .T h e reliability measu rements are also conducted and the PA has an estimated lifetime of 80613 hours.