A Process-V ariation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM Daeyong Shim, Hyunsik Jeong

Abstract

Smaller transistors mean that capacitors are charged less uniformly, which increases the self-refresh current in the DRAMs used in mobile devices. Adaptive self-refresh using an on-chip thermometer can solve this problem. We propose an on-chip CMOS thermometer speci fically designed for controlling the refresh period of a DRAM. This thermometer includes a novel temperature sensor which has been implemented and integrated into an LPDDR2 chip. The LPDDR2 chip is fabricated in a 44-nm DRAM process. The sensor has a temperature sensitivity of 3.2 mV C, over a range of 0 Ct o1 1 0 C. Its resolution is 1.94 C and is only limited by the 6.2-mV step of the associated resistor ladder not by its own design. The linearity of the sensor permits one-point calibration, after which the error si n6 1s a m p l e circuits ranged between 1.42 Ca n d 2.66 C .T h es e n s o rh a s an active area of 0.001725 mm and consumes less than 0.36 W on average with a supply of 1.1 V. At its lowest op erating temper- ature, this thermometer reduc es the IDD6 current of the LPDDR2 chip by almost half.