← 返回 JSSC 论文列表
📄 下载 JSSC 原文 PDF
JSSC 2013第10期Memory65nmSRAM

A Sub-03 V Area-Ef ficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Sch

提出一种L形7T SRAM单元和读位线摆动扩展方案，用于降低最小工作电压并优化面积效率。
260 mV VDDmin，面积效率优于传统8T SRAM约50%
SRAM低电压面积效率读位线摆动65nm工艺
▸L形7T SRAM单元设计
▸读位线摆动扩展方案（RBL-EXPD）
▸不对称阈值电压的1T读端口（AV-1TRP）
Abstract
In previous SRAM designs, reducing minimum op- erating voltage (VDDmin) inevitably resulted in device sw i t ha large cell area (A). This work proposes an L-shaped 7T cell (L7T) and read-bitline (RBL) swing expansion scheme (RBL-EXPD) to minimize A VDDmin for low-voltage applications. T his L7T features an area-ef ficient cell layout and a read-disturb free de- coupled 1T read port (RP) capable of providing a wide space for write margin improvement. The RBL-EXPD emplo ys (1) boosted RBL (BRBL), (