A Sub-0.3 V Area-Ef ficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V Read-Port, and Offset Cell VDD Biasing Techniques Meng-Fan Chang, Ming-Pin Chen, Lai-Fu Chen, Shu-Meng Y ang, Y ao-Jen Kuo, Jui-Jen Wu, Hsiu-Y un Su, Y uan-Hua Chu, Wen-Ching Wu, Tzu-Yi Y ang, and Hiroyuki Y amauchi

Abstract

In previous SRAM designs, reducing minimum op- erating voltage (VDDmin) inevitably resulted in device sw i t ha large cell area (A). This work proposes an L-shaped 7T cell (L7T) and read-bitline (RBL) swing expansion scheme (RBL-EXPD) to minimize A VDDmin for low-voltage applications. T his L7T features an area-ef ficient cell layout and a read-disturb free de- coupled 1T read port (RP) capable of providing a wide space for write margin improvement. The RBL-EXPD emplo ys (1) boosted RBL (BRBL), (2) 1T-RP with asymmetric-V ,( A V - 1 T R P )a n d (3) offset cell-VDD biasing (OFS-CVDD) to expand RBL swing in both the upward and downward directions sec uring both ‘High’ and ‘Low’ sensing margins. A 65 nm 256-row 32 Kb L7T SRAM macro-fabricated using BRBL and A VTH-RP achieved a 260 mV VDDmin. The resulting A VDDmin is ~50 % lower than that of conventional 8T SRAM devices.