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JSSC 2013第10期RF & Wireless130nm CMOS

Design and Analysis of Harmonic Rejection Mixers With Programmable LO Frequency Travis Forbes, Student Member , IEEE, Wei-Gi Ho, and Ranjit Gharpurey ,S e n i or Member , IEEE

提出一种具有可编程LO频率的谐波抑制混频器设计,实现多频率合成与高谐波抑制。
11.9dB增益, 11.2dB DSB NF, 5.4dBm IIP3, >61dB HR3/5/7, 67mW@1.2V
谐波抑制混频器可编程LO多相位时钟CMOS频率合成
创新点1:可编程LO频率生成技术(电路创新)。通过单一主时钟频率生成多个有效LO频率,无需修改模拟信号路径,实现了LO频率的灵活配置,支持八种有效LO频率合成,显著提升了系统适应性。
创新点2:两阶段HRM时钟方案降低失配敏感度(方法创新)。采用分阶段时钟控制策略,有效减少了增益和相位失配的影响,实测谐波抑制比(HR3/5/7)分别达到72dB、71dB和67dB,无需校准。
创新点3:无校准/谐波滤波实现高谐波抑制(系统创新)。通过优化的多相混频器架构和时钟分配网络,在未使用校准或外部滤波的情况下,实现了>61dB(LO因子2-6)和54dB(LO因子7)的谐波抑制性能。
创新点4:宽频带输入匹配设计(电路创新)。在50-830MHz范围内实现S11<-10dB的宽带输入匹配,结合67mW低功耗(1.2V供电),展现了优异的射频前端综合性能。
Abstract
A harmonic rejection mixer (HRM) with a pro- grammable local oscillator (LO) frequency is presented. The design allows for the generation of multiple effective LO frequen- cies within a single HRM that are derived from a single primary clock frequency, without any modi fications to the analog signal path. A 16-phase HRM with the pro posed frequency synthesis technique is implemented in a 130-nm CMOS process. A clocking approach within a two-stage HRM is presented, which reduces HRM sensitivity to both gain and phase mismatch. The HRM syn- thesizes eight effective LO frequencies and shows an 11.9-dB gain, 11.2-dB DSB NF, and 5.4-dBm in-band IIP3 in the fundamental mode. Greater than 72-dB HR3, 71-dB HR5, and 67-dB HR7 is achieved over ten IC samples in this mode without calibration or harmonic filtering. Harmonic rejection greater than 61 dB for LO factors 2–6 and 54 dB for LO factor 7 is observed, when modifying the effective LO frequency. The HRM achieves S11 better than 10 dB over 50–830 MHz and has a total power consumption of 67 mW from a 1.2-V supply.