InP HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-to-Analog Converter With > 70-dB SFDR Bert Oyama, Daniel Ching, Khanh Thai, Augu sto Gutierrez-Aitken, and Vipul J. Patel , Member , IEEE

Abstract

A prototype 13-b 1.33-Gsps digital-to-analog con- verter (DAC) implemented in a uni que heterogeneous integration process (combining 0.45-µm InP HBT with 0.18-µm CMOS) is presented. Measured performance of greater than 70 dB SFDR is achieved across a 500-MHz bandwidth centered at 1 GHz (second Nyquist band). Heterogene ous integration enables each circuit element to be implemente d in the transistor technology best suited to the circuit functi on. Low dc power is achieved by implementing the digital front-end in a standard silicon CMOS technology, while InP HBT tech nology is used to implement the high-speed/high-precision current-steering DAC core. The core DAC employs a segmented architecture with three unary most significant bits and an R-2R ladderf o rt h et e nl e a s ts i g n ificant bits. No calibration circuitry is requ ired to achieve better than 11 b of dc linearity. Dynamic performance is enhanced by employing an ultra-high-linearity return-to-zero (RZ) analog output deglitcher switch. Measured performance data for three different circuit design variations of the output sw itch (incorporating a varying mix of CMOS and InP HBT devices) is presented.