A 0.1–1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using

Abstract

This paper presents a digital-to-phase converter (DPC) with 8-bits of resolution and a wide frequency range for the input/output clocks. A harmonic rejection (HR) filter is introduced to improve linear ity across a frequency range of 0.1–1.5 GHz. Instead of using tim e-domain averaging of phase interpolators (PI) in a conventi onal DPC, the frequency-domain filter directly cancels the 3rd- and 5th-order harmonics of the phase interpolated signal. The architecture is designed using an inverter-based PI circuit structure to improve power consumption and area. The inverter nonlinearity is improved using resistive averaging. The residual INL and DNL are further reduced by nonlinear weighting of the interpolation. Designed and fabricated in 65-nm CMOS technology, the DPC demonstrates a maximum INL and DNL of 1.33 and 0.52 LSB while consumes a power of 4.3 mW and occupies 0.06 mm² area.