← 返回 JSSC 论文列表JSSC 2013第11期Data Converters40nmSAR ADC
A 05-V 52-fJConversion-Step Full Asynchronous SAR ADC With Leakage Power Reducti
提出一种超低功耗和超低电压的全异步SAR ADC，通过泄漏功率降低技术显著提升能效。
40nm CMOS, 0.5V, 4MS/s, 8.2-bit ENOB, 650pW@0.1kS/s
SAR ADC超低功耗异步设计泄漏功率阈值电压优化
▸创新点1：全异步操作技术通过消除时钟同步需求，显著降低动态功耗并提升转换效率，在0.5V电源电压下实现650pW超低功耗，属于系统级创新。
▸创新点2：增强型自供电门控技术动态切断闲置模块电源，结合40nm工艺实现98%静态漏电功耗削减，属于电路级功耗优化创新。
▸创新点3：高低阈值MOSFET混合设计在保持最大采样频率4MS/s的同时优化漏电，Vth选择策略属于器件级工艺创新。
▸创新点4：0.4-0.7V宽电压自适应架构支持功耗-性能动态调节，在0.5V时达5.2fJ/step能效比，属于电源域系统创新。
Abstract
This paper presents an ultralow-power and ul-
tralow-voltage SAR ADC. Full asynchronous operation and
boosted self-power gating are proposed to improve conversion
accuracy and reduce static leakage power. By designing with
MOSFET of high threshold voltage
and low threshold
voltage , the leakage power is reduced without decrease
of maximum sampling frequency. The test chip in 40-nm CMOS
process has successfully redu ced leakage power by 98%, and
it achieves 8.2-bit ENOB and while consuming only 6