A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Tre

Abstract

This paper presents a multiple code-rate turbo de- c o d e ru s i n gt h er e c i p r o c a ld u a lt r e l l i st oi m p r o v et h eh a r d w a r ee f - ficiency. For a convolutional code with code rate ,i t sc o r - responding reciprocal dual code with rate has smaller codeword space than the original code while , leading to a simplified trellis of the high code -rate code. The proposed decoder architecture can decode code rate constituent convo- lutional codes for , 2, 4, 8, and 16. Moreover,