A Broadband Stacked Power Ampli fier in 45-nm CMOS SOI Technology Jing-Hwa Chen, Student Member , IEEE, Sultan R. Helmi , Student Member , IEEE, Reza Azadegan

Abstract

A fully integrated broadband power ampli fier( P A ) is implemented in a standard 45-nm CMOS SOI technology. The PA is designed using a dynamically biased stacked SOI transistor approach, which constructively adds drain–s ource voltage signals of individual transistors while ke eping their gate voltages within source and drain voltage limits. The design overcomes both low gate-oxide breakdown and low source-drain reachthrough voltages of nanoscale CMOS transistors. The number, size, and topology of transistors in the stack are optimized to deliver a relatively high linear output power over a wide range of f requencies. The ampli- fier under a supply voltage of 4.5 V measures a flat gain of 6 dB with 1-dB bandwidth of 6 to 26.5 GHz ( -band to -band). At 18 GHz, the PA under a supply voltag eo f7 . 2Vm e a s u r e sas a t - urated output power of 26.1 dBm ( 400 mW), a linear output power of 22.5 dBm, and a peak power-added ef fi- ciency (PAE) of 11%. With a lower power supply voltage of 4.5 V , the PAE increases to more than 20% and stays above 17% with rel- atively constant and for several measured frequen- cies in the range of 6 to 20 GH z. The PA occupies an active chip area of only 0.16 mm .