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A Broadband Stacked Power Ampli fier in 45-nm CMOS SOI Technology Jing-Hwa Chen S
45nm CMOS SOI技术中的宽带堆叠功率放大器设计
6-26.5 GHz带宽，26.1 dBm饱和输出功率，11%峰值PAE
功率放大器CMOS SOI宽带堆叠晶体管动态偏置
▸动态偏置堆叠SOI晶体管方法
▸宽频带高线性输出功率优化
▸克服纳米级CMOS晶体管的低栅氧击穿和低源漏穿透电压
Abstract
A fully integrated broadband power ampli fier( P A )
is implemented in a standard 45-nm CMOS SOI technology. The
PA is designed using a dynamically biased stacked SOI transistor
approach, which constructively adds drain–s ource voltage signals
of individual transistors while ke eping their gate voltages within
source and drain voltage limits. The design overcomes both low
gate-oxide breakdown and low source-drain reachthrough voltages
of nanoscale CMOS transistors. The number, size, and topology