← 返回 JSSC 论文列表JSSC 2013第11期Clocking & PLLs0.13μmPLLNeural Network Accelerator
A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fract
1GHz分数N锁相环采用FIR嵌入式相位插值器实现噪声滤波，降低相位噪声34dB。
0.13μm CMOS, 16.8mW功耗, 3.2MHz带宽, 106dBc@100kHz带内噪声, 107.5dBc@6MHz带外噪声
分数N锁相环FIR滤波相位插值器噪声抑制宽带宽
▸FIR嵌入式相位插值器噪声滤波方案
▸双参考插值方案补偿系统非线性
▸多重双参考插值提高输入种子相位失配免疫力
Abstract
This paper presents a 1-GHz fractional-N PLL
with a noise- filtering scheme using a FIR-embedded phase inter-
polator. The proposed dual-referenced interpolation scheme com-
pensates for systematic nonlinearity in circuit operation and in-
creases immunity to mismatches in input seed phases. By multiple
use of a dual-referenced interpolator, the phase interpolator real-
izes an embedded FIR filtering for the quantization noise from the
modulator. The implemented PLL in 0.13- mC M O Sc o n -
sumes