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A Low-Power 0566 Gbs Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs Jafar
一种嵌入低成本28nm FPGA的低功耗0.5-6.6 Gb/s自适应四通道收发器设计
28nm CMOS, 1.2V/1V, 6.6Gb/s, 20dB损耗通道BER<10^-12, 129mW
低功耗收发器自适应均衡FPGA集成时钟恢复高速串行接口
▸集成技术支持线键合和倒装芯片封装
▸采用3级CTLE和LMS算法实现全自适应接收前端
▸双宽范围环形PLL提供增强时钟灵活性
Abstract
This paper describes the design of a 0.5–6.6 Gb/s
fully-adaptive low-power quad transceiver embedded in
low-leakage 28 nm CMOS FPGAs. Integration techniques enable
the utilization of the transceiver in FPGAs with both wire-bond
and flip-chip packages and resolve signi ficant challenges with
receiver input and transmitter output insertion loss, power in-
tegrity, ESD, and reliability. T he transceiver clocking network
provides continuous operation range up to the maximum speed
and incorporates two