A Low-Power 0.5–6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs

Abstract

This paper describes the design of a 0.5–6.6 Gb/s fully-adaptive low-power quad transceiver embedded in low-leakage 28 nm CMOS FPGAs. Integration techniques enable the utilization of the transceiver in FPGAs with both wire-bond and flip-chip packages and resolve signi ficant challenges with receiver input and transmitter output insertion loss, power in- tegrity, ESD, and reliability. T he transceiver clocking network provides continuous operation range up to the maximum speed and incorporates two wide-range ring-based PLLs for enhanced clocking flexibility. The receiver front-end utilizes a 3-stage CTLE with wide input common-mode to remove the post-cursor ISI. The CTLE is fully adaptive using an LMS algorithm and edge-based equalization. The transmitter uti lizes a 3-tap FIR. The transceiver achieves BER 10 at 6.6 Gb/s over a 20 dB loss channel. Power consumption is 129 mW from 1.2 V and 1 V supplies.