JSSC 2013第11期Clocking & PLLs90nmDelta-Sigma ADCPLL

A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO Yingchieh

近阈值480 MHz全数字PLL，采用自举DCO实现低功耗设计。

90nm CMOS, 0.5V, 480MHz, 78µW

近阈值全数字PLL自举DCO低功耗Σ-Δ调制器

▸9位自举DCO降低电源电压和功耗

▸加权热敏电阻网络实现高线性度

▸4位Σ-Δ调制器通过抖动提高分辨率

Abstract

This paper presents a ne ar-threshold low-power all-digital PLL (ADPLL). It includes a 9-bit bootstrapped DCO (BDCO) to reduce supply vol tage and power consump tion, a weighted thermometer-controlled resistor network (WTRN) to achieve high linearity, and a 4-bit sigma-delta modulator to improve the resolution through ditherin g. The ADPLL is fab- ricated in a 90 nm SPRVT low-K CMOS process with a core area of 0.057 mm². The measured results demonstrate that the bootstrapped ring oscillator (BTR