A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM Sami Rosenblatt, Srivatsan Chellappa, Alberto Cestero, Norman Robson

Abstract

An architecture for enabling self-authenticating chips uses 4 Kb electrically programmable fuses (eFUSE) to store bit strings representing encrypted intrinsic fingerprints obtained by offset-superimposing six out of one thousand 4 Kb domains ran- domly chosen in 4 Mb embedded DRAM. Authentication is accom- plished by regenerating various encrypted intrinsic fingerprints, which are then compared with the bit strings in the eFUSE. Monte Carlo simulations demonstrate that, targeting an average of 32 re- tention fails per domain, the strings are unique and authentication is statistically guaranteed without bit correction even when un- stable bits are introduced. The preliminary results are con firmed in > 50 parts containing 4 Mb memory implemented in 22-nm SOI hardware under the target voltage ±10% conditions. The analyt- ical model predicts > 10 years to crack the encryption by brute force, while satisfying > 99.9999% su ccessful authentication for one million parts.