Instruction-Cycle-Based Dynamic V oltage Scaling Power Management for Low-Power

Abstract

This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-pow er processor designs. The pro- posed iDVS technique is fully compatible with conventional DVS scheduler algorithms. An addition al computer aided design-based design flow was embedded in a standard cell library to implement the iDVS-based processor in highl y integrated system-on-a-chip applications. The lattice asynchronous self-timed control digital low-d