Instruction-Cycle-Based Dynamic V oltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings Shen-Y u Peng, Tzu-Chi Huang , Student Member , IEEE ,Y u - H u e i L e e, Student Member , IEEE , Chao-Chang Chiu, Student Member , IEEE,K e - H o r n g C h e n, Senior Member , IEEE, Ying-Hsi Lin, Chao-Cheng Lee, Tsung-Y en Tsai, Chen-Chih Huang, Long-Der Chen, and Cheng-Chen Y ang

Abstract

This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-pow er processor designs. The pro- posed iDVS technique is fully compatible with conventional DVS scheduler algorithms. An addition al computer aided design-based design flow was embedded in a standard cell library to implement the iDVS-based processor in highl y integrated system-on-a-chip applications. The lattice asynchronous self-timed control digital low-dropout regulator with swift response and low quiescent cur- rent was also utilized to improve iDVS voltage transition response. Results show that the iDVS-based processor with the proposed adaptive instruction cycle control scheme can ef ficiently perform millions of instructions per sec ond during iDVS transition. The iDVS-based digital signal processor chip was implemented in a HH-NEC 0.18-µm standard complementary metal-oxide semicon- ductor. Measurement results show that the voltage tracking speed with 11.6 V/µs saved 53% power.