A 100 MHz 82.4% Ef ficiency Package-Bondwire Based Four-Phase Fully-Integrated Buck Converter With Flying Capacitor for Area Reduction Cheng Huang, Student Member , IEEE, and Philip K. T. Mok , Senior Member , IEEE

Abstract

In today’s fully-integrated converters, the integrated LC components dominate the chip-area and have becom et h e major limitation of reducing the cost and increasing the current density. This paper presents a 100 MHz four-phase fully-inte- grated buck converter with standard packag eb o n d w i r ei n d u c t o r s and a flying capacitor (C ) topology for chip-area reduction, occupying 1.25 mm² effective area in 0.13-µm CMOS technology. A four-phase operation is introduced for chip-area reduction with the cost penalty minimized by utilizing standard package bondwire inductance as power inductors. Meanwhile, an extra more than 40% chip-area saving is a chieved by the simple but ef- fective C topology to take advantage of the parasitic bondwire inductance at the input for rippl e attenuation. A maximum output current of 1.2 A is obtained by th e four-phase operation, while only 3.73 nF overall integrated capacitors are required. Also, with the chip-area hungry integrated spiral metal inductors eliminated, the current density is signi ficantly increased. 0.96 A/mm² current density and 82.4% efficiency is obtained with 1.2 V to 0.9 V voltage conversion without using any off-chip inductors or advanced pro- cesses. The reliability is also verified by measurement with various bondwire inductances and con figurations.