← 返回 JSSC 论文列表JSSC 2013第12期RF & Wireless40nmFlash ADC
A 103-GSs 6-Bit Flash ADC for 10G Ethernet Applications Aida V arzaghani Member
一款用于10G以太网应用的103-GSs 6位闪存ADC设计
40nm CMOS, 0.9V, 10.3GS/s
闪存ADC10G以太网DSP接收器校准DACWallace树编码
▸创新点1：4路交错ADC设计（系统创新）。通过4路并行采样架构实现10.3GS/s超高采样率，采用前端可变增益放大器(VGA)驱动多组T/H开关，解决了单通道带宽限制问题，支持3.5-6GHz宽频带信号处理。
▸创新点2：Wallace树加法器编码（电路创新）。采用并行压缩结构的Wallace-tree作为温度计码至二进制编码器，支持比较器动态重排序和冗余设计，显著降低编码延迟并提升6位量化精度下的时序容限。
▸创新点3：集成8位校准DAC（方法创新）。内置高精度DAC提供参考电压，通过闭环校准消除信号路径累积偏移，同时补偿精细VGA和电阻梯的非线性误差，使SNDR提升至34dB。
▸创新点4：0.9V超低电压供电（电路创新）。在40nm CMOS工艺下实现全系统0.9V供电，通过优化时钟路径和比较器阵列功耗，在242mW总功耗下达成0.27mm²的紧凑面积。
Abstract
This paper presents the design of a 40-nm CMOS
10.3-GS/s 6-bit Flash ADC used as the analog frontend of a
universal DSP-based receiver that meets the requirements for
all the NRZ 10G Ethernet (10GE) standards, for both fiber and
copper channels. The 4-way interleaved ADC consists of a pair
of frontend variable gain ampli fiers (VGAs) driving four sets of
track-and-hold (T/H) switches, followed by fine VGAs that drive
6-bit comparator arrays. A Wallac e-tree adder is utilized as the
thermometer-to-b