A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson–Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS

Abstract

Tomlinson–Harashima (TH) precod ing is a trans- mitter equalization technique in which the post-cursor intersymbol interference (ISI) is canceled by means of an in finite impulse response (IIR) filter with modulo (MOD)-ba sed amplitude lim- itation. TH equalizers are suited for asymmetric links, such as DRAM interfaces, where the transmitter contains the equalization complexity and the receiver is kept s imple. To increase the data rate, we propose the application of pipelining and half-rate opera- tion to the ISI subtraction in the equalizer’s feedback path. A TH equalizer with 8 taps, 6 bit resolu tion, and 2-PAM/4-PAM support has been implemented in 22-nm sili con-on-insulator (SOI) CMOS technology. In measurements, the feedback delay reduction tech- niques allow us to equalize 3 4-cm-long PCB traces having 12-dB loss with 7 ISI reduction for 5.0-Gb/s 2-PAM signaling, and in 10.0-Gb/s 4-PAM mode completely closed eye diagrams are opened. The measured ef ficiency of the 145 m 115 mt r a n s - mitter is 1.2 pJ/bit in 4-PAM mode at 5.0 Gbaud with disabled equalization and increases linearly with 14 W/Gbaud per 1% increase of the equaliza tion tap weights.