A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step

Abstract

This paper presents a power-efficient 10/12 bit 40 kS/s SAR ADC for sensor applications. It supports resoluti ons of 10 and 12 bit and sample rates from DC up to 40 kS/s to accommo- date a variety of sensor applicatio ns. A Data-Driven Noise-Reduc- tion method is introduced to selectively enh ance the comparator noise performance. In this way, a higher ADC resolution can be achieved with a small increase of the power consumption. A self-os- cillating comparator is used to generate t he bit-cycling clock inter- nally. In this way, the ADC only requires an external clock at the sample-rate frequency. A segmented capacitive DAC with 250 aF unit elements is applied to save powe r and to reduce DNL errors at the same time. The implemented prototype in 65 nm CMOS oc- cupies an area of 0.076 mm . For the two supported resolutions (10/12 bit), the ADC achieves an EN OB of 9.4 and 10.1 bit while consuming 72 and 97 nW from a 0.6 V supply at 40 kS/s. This leads to power efficiencies of 2.7 and 2.2 fJ/conversion-step for 10 bit and 12 bit resolution, respectivel y. Furthermore, the leakage power, which is below 0.4 nW, ensures that the ef ficiency can be main- tained down to very low sample rates.