JSSC 2013第12期Data Converters65nmSAR ADCDAC

A 14b 80 MSs SAR ADC With 736 dB SNDR in 65 nm CMOS Ron Kapusta Senior Member I

一款14位80 MS/s SAR ADC，采用65nm CMOS工艺，实现73.6 dB SNDR和31.1 mW功耗。

65nm CMOS, 1.2V, 80MS/s, 73.6 dB SNDR, 31.1 mW

SAR ADC高精度高速低功耗电荷重分配

▸使用闪存子ADC快速解析5个MSB

▸DAC操作时间交错以提升速度

▸全片上DAC电荷重分配大幅减少建立时间

Abstract

A 14-bit SAR ADC is presented that achieves 73.6 dB SNDR at 80 MSPS while using a 1.2-V-only supply. In order to overcome throughput limitations common to conventional SAR ADCs, several techniques are proposed. First, a ﬂash sub-ADC is utilized to resolve the 5 MSBs quickly prior to SAR sequential decisions of the LSBs. Second, the DAC operation is time-inter- leaved by a factor of 2, increasing speed while allowing a single comparator to be shared between all DACs. Third, fully on-chip DAC char