JSSC 2013第12期Data Converters0.6 µm BiCMOSDAC

A 20b Clockless DAC With Sub-ppm INL 75 nVHz Noise and 005 ppmC Stability

一款20位无时钟DAC，具有亚ppm级INL、75nVHz噪声和0.05ppm/°C稳定性

0.33 ppm INL, 7.5 nV/√Hz噪声, ±10 V输出范围, 1 µs建立时间

高精度DAC无时钟架构电阻分压器温度稳定性噪声优化

▸6b并行电阻分压器与14b R-2R子DAC架构

▸单电流输出校准DAC校正电阻失配和非线性

▸力和感应开关拓扑克服CMOS开关电阻

Abstract

This paper presents a 20b clockless DAC designed for precision calibrated systems. The architecture is a 6b parallel re- sistor voltage divider with a 14b R-2R subDAC. This architecture is inherently good for noise and tempe rature stability. Major causes of nonlinearity are discussed. A sin gle current-output calibration DAC corrects for both random resistor mismatch and systematic resistor nonlinearity. A force and sense switch topology overcomes I N Lf r o mC M O Ss w i t c hr e s i s t a n c