A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability Roddy C. McLachlan, Alan G illespie, Michael C. W. Coln , Member , IEEE, Douglas Chisholm, and Denise T. Lee

Abstract

This paper presents a 20b clockless DAC designed for precision calibrated systems. The architecture is a 6b parallel re- sistor voltage divider with a 14b R-2R subDAC. This architecture is inherently good for noise and tempe rature stability. Major causes of nonlinearity are discussed. A sin gle current-output calibration DAC corrects for both random resistor mismatch and systematic resistor nonlinearity. A force and sense switch topology overcomes I N Lf r o mC M O Ss w i t c hr e s i s t a n c e .T h eD A Ci si m p l e m e n t e di na 0.6 µm 30 V BiCMOS process with 5 V CMOS devices and Si-Cr thin-film resistors. It achieves 0.33 ppm INL and 7.5 nV/ √Hz noise with a ±10 V output span. It has 0.05 ppm/°C temperature stability and settles in 1 µs. Current con sumption is 4.2 mA from 30 V sup- plies, excluding power required for external reference buffers.