← 返回 JSSC 论文列表JSSC 2013第12期Data Converters32nmSAR ADCDAC
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS Lukas Kull, Student Member , IEEE, Thomas Toi fl, Senior Member , IEEE
32nm CMOS工艺下实现的8位1.2 GS/s异步SAR ADC，采用双比较器交替工作和冗余电容DAC技术，功耗31mW。
8bit 1.2GS/s, 39.3dB SNDR, 34fJ/step FoM, 31mW@1V
SAR ADC高速比较器电容DAC背景校准低功耗
▸创新点1：双比较器异步交替工作（方法创新）。通过两个交替工作的比较器实现高速采样，每个比较器独立工作于异步时钟，有效提升转换速率至1.2 GS/s，同时降低时序冲突风险。
▸创新点2：冗余电容DAC恒定共模技术（电路创新）。采用冗余电容DAC结构并保持恒定共模电压，显著提升比较器精度，支持39.3 dB SNDR的高信噪比性能。
▸创新点3：堆叠式CDAC结构节省面积（电路创新）。通过电容DAC（CDAC）与参考电容的堆叠设计，减少布局面积至0.0015 mm²，同时优化建立速度，适合纳米级工艺（32 nm CMOS）。
▸创新点4：低功耗时钟参考缓冲器（系统创新）。集成时钟控制的电容参考缓冲器，结合分数参考电压技术，降低DAC单元电容数量，实现仅3.1 mW的超低功耗（1 V电源）。
Abstract
An 8b 1.2 GS/s single-channel Successive Approx- imation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step. High-speed operation is achieved by converting each sample with two alternate comparators clocked asynchro- nously and a redundant capacitive DAC with constant common mode to improve the accuracy of the comparator. A low-power, clocked capacitive reference buffer is used, and fractional refer- ence voltages are provided to reduce the number of unit capacito rs in the capacitive DAC (CDAC). The ADC stacks the CDAC with the reference capacitor to reduce the area and enhance the settling speed. Background calibration of comparator offse ti s implemented. The ADC consumes 3.1 mW from a 1 V supply and occupies 0.0015 mm².