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JSSC 2013第12期Clocking & PLLs65nm

A Class-F CMOS Oscillator

提出一种基于F类振荡器的新型拓扑结构,通过优化相位噪声转换机制实现更低的相位噪声和更高的功率效率。
5.9–7.6 GHz调谐范围,3 MHz偏移处相位噪声-136 dBc/Hz,功耗12 mA@1.25V
F类振荡器相位噪声CMOS变压器耦合谐波调谐
利用时间变相位噪声模型优化相位噪声转换机制
通过变压器实现辅助阻抗峰值以增强三次谐波
降低有效脉冲灵敏度函数(ISF)从而减少振荡器噪声因子
Abstract
An oscillator topology demonstrating an improved phase noise performance is propo sed in this paper. It exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The proposed oscillator is based on enforcing a pseudo-square voltage waveform around the LC tank by increasing the third-harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled res