A 130.7-mm 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology

Abstract

A 32-Gb ReRAM test chip has been developed in a 24-nm process, with a diode as the selection device and metal oxide as the switching element. The memory array is constructed with cross-point architecture to allow multiple memory layers stacked above the supporting circuitry and minimize the circuit area overhead. Die ef ficiency is further improved by sharing wordlines and bitlines between adjacent blocks. As the number of sense amplifiers under the memory array is limited, a pipelined array control scheme is adopted to comp ensate the performance impact while utilizing the fast switching time of ReRAM cells. With the chip current consumption bein g dominated by the array leakage and sensitive to array bias and operating conditions, a charge pump stage control scheme is introduced to dynamically adapt to the operating conditions for optimal power consumption. Smart Read during sensing and leakage current compensation scheme during programming are applied to the large-block architecture and achieve a chip density that is several orders of magnitude higher than prior ReRAM developments.