A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications Mehul Tikekar, Student Member , IEEE

Abstract

High Ef ficiency Video Coding, the lates tv i d e os t a n - dard, uses larger and variable-sized coding units and longer interpolation filters than H.264/A VC to better exploit redundancy in video signals. These algorithmic tech niques enable a 50% de- crease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper desc ribes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes—a 32% reduction. A high-th roughput read-only cache combined with DRAM-latency-a ware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity con figuration and occupies 1.77 mm in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 nJ/pixel of normalized system power.