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A 249-Mpixels HEVC Video-Decoder Chip for 4K Ultra-HD Applications Mehul Tikekar
一款支持4K超高清的HEVC视频解码芯片，优化架构降低存储需求
40nm CMOS, 200MHz, 1.19nJ/pixel, 4K Ultra HD 30-fps
HEVC视频解码4K超高清低功耗ASIC
▸两阶段子流水线方案减少片上SRAM
▸高吞吐只读缓存结合DRAM延迟感知内存映射
▸针对HEVC低复杂度配置优化
Abstract
High Ef ficiency Video Coding, the lates tv i d e os t a n -
dard, uses larger and variable-sized coding units and longer
interpolation filters than H.264/A VC to better exploit redundancy
in video signals. These algorithmic tech niques enable a 50% de-
crease in bitrate at the cost of computational complexity, external
memory bandwidth, and, for ASIC implementations, on-chip
SRAM of the video codec. This paper desc ribes architectural
optimizations for an HEVC video decoder chip. The chip uses
a