JSSC 2014第1期Memory28nmSRAM

A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable

提出双电源SRAM的电路技术，显著降低活动与待机模式功耗

28nm CMOS, 活动模式功耗降低27%, 待机模式功耗降低85%

双电源SRAM功耗优化位线功率计算待机模式28nm CMOS

▸使用位线功率计算器自适应调节活动模式单元供电电压

▸数字可控保持电路在待机模式下实现低控制功耗

▸28nm CMOS工艺实现双电源SRAM

Abstract

This paper presents circuit techniques to reduce both active and standby mode power, especially at room temperature (RT). A bit-line power calculator is used to adaptively set the cell supply voltage in the active mode. A digitally controllable retention circuit regulates in the standby mode with small con- trol power. These circuits are implemented in a dual-power-supply SRAM in 28-nm CMOS technology. Compared with the conven- tional scheme, the power consump tion in the active and standby mode at 25 C is reduced by 27% and 85%, respectively.