A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13- m CMOS for Nonvolatile Processing in

Abstract

In order to realize a digital system with no distinction between “on” and “off,” the computational state must be stored in nonvolatile memory elements. If the energy cost and time cost of managing the computational state in nonvolatile memory can be lowered to the microsecond and p icojoule-per-bit level, such a system could operate from unre liable harvested energy, never requiring a reboot. This work presents a nonvolatile D- flip-flop ( N V D F F )d e s i g n e di n0 . 1 3 - m CMOS that retains state in ferro- electric capacitors during sporadic power loss. The NVDFF is in- tegrated into an ASIC design flow, and a test-case nonvolatile FIR filter with an accompanying powe r management unit automati- cally saves and restores the state based on the status of a one-bit indicator of energy availability. Correct operation has been veri- fied over power-cycle intervals from 4.8 s to 1 day. The round-trip save-restore energy is 3.4 pJ per NVDFF. Also presented are sta- tistical measurements across 21 000 NVDFFs to validate the capa- bility of the circuit to achieve the requisite 10-ppm failure rate for embedded system applications.