A 36 GHz 16-Core SPARC SoC Processor in 28 nm

Abstract

T h e3 . 6G H zS P A R CT 5p r o c e s s o ri sO r a c l e ’ sn e x t generation CMT SoC processor implemented in TSMC’s 28 nm process with 1.5 billion transistors. Signi ficant performance improvements were made by doubling the previous generations number of cores to 16 and L3 cache size to 8 MB while increasing bandwidth by nearly 3×. Power ef ficiency was improved through features like DVFS, core-pair cycle skipping and SerDes power scaling. The SPARC T5 processor has been designed to fiti n sys