A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm Jason M. Hart , Member , IEEE, Hoyeol Cho, Y uefei Ge, Gr egory Gruber

Abstract

T h e3 . 6G H zS P A R CT 5p r o c e s s o ri sO r a c l e ’ sn e x t generation CMT SoC processor implemented in TSMC’s 28 nm process with 1.5 billion transistors. Signi ficant performance improvements were made by doubling the previous generations number of cores to 16 and L3 cache size to 8 MB while increasing bandwidth by nearly 3×. Power ef ficiency was improved through features like DVFS, core-pair cycle skipping and SerDes power scaling. The SPARC T5 processor has been designed to fiti n systems that can scale from 1 to 8 sockets, or 128 to 1024 threads, in glueless fashion. The diverse system-level bandwidth require- ments of up to 5.65 TB/sec in these systems are met by advanced SERDES design that handles up to 30 dB loss in an area and power ef ficient manner. The different thermal envelopes of these systems are addressed by power management features that span software, system and chip design.