A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory

Abstract

This paper describes an asymmetric 6.4-Gb/s memory interface for a wide range of DIMM configurations for desktop and server applications. The link uses a fly-by quadrature forwarded clock to enable fast startup and power-mode transitions on the DRAM and per-bit timing adjustme nt on the controller to enable the high-speed signaling. Single-ended low-swing near-ground sig- naling (NGS) is introduced in order to minimize signaling power. Transmitter and receiver equalization are used on the controller, but not the DRAM, in order to save DRAM complexity and power. Architectural and circuit techniques are presented to address the complex signaling and timing environment encountered in the explored con figurations. The implement ed link achieves 6.4-Gb/s communication over a 3.5-in FR4 PCB trace with a dual-rank dual-in line memory module with better than 9.1-pJ/bit power efficiency for the entire chip.